My Dream Skylake-E Platform from Intel

Background Information

 

This is mostly intended as a post for computer enthusiasts, and I’m going to go relatively quickly, as this post would be even longer if I had to explain all my background information. If you have any questions, feel free to raise them in the comments.

 

I have been considering the optimal design for an enthusiast CPU High End Desktop (HEDT) platform would look like. I think that one of the unfortunate things is that we enthusiasts have been left out for the past couple of generations.  We have not been given the kind of top priority that aligns with what we are looking for, which is maximum single threaded performance at all costs.  I think that Intel sees enthusiasts as just a small group of people that although more profitable than the common user, does not command the margins of servers and never really gave the attention that we wanted. They also seem to see us (unfortunately) for milking.

 

For the past couple of generations, Intel has been releasing about 10% increments with each generation, after Conroe, which achieved a huge gain over the failed Netburst architecture (which hit thermal limits and could not meet the intended clockspeed targets).  I think that at this point, we are facing the laws of physics here and the limits of silicon. Barring something radical, such as quantum computer or perhaps even the widespread production of a graphene transistor (currently there is the band-gap issue and several other key technical problems including how to scale up production), we are facing the limits of what modern silicon can do. In the immediate future, we are looking at moderate incremental steps like 10% every two generations and perhaps the migration to III-V materials. Other technologies such as EUV seem to be problem plagued, which puts smaller node shrinks into question.

 

The end result has been slower than desired gains and for enthusiasts, we have been rather underwhelmed. Skylake is currently Intel’s latest CPU architecture.   Skylake is actually a pretty decent upgrade all things considered. We have seen perhaps ~8-10% gains clock for clock.  Anyways, here is Anandtech’s review. Actually, for the overclocking community the gains are even smaller because Skylake seems to overclock between about 4.6-4.8 Ghz, versus 4.7-4.9 on Haswell’s Devil’s Canyon.  A few super-fast Devil’s Canyon 4790Ks could overclock to around 5 GHz and a few of the Skylake 6700Ks can do up to 4.9 GHz.

 

However, it is the HEDT platform I would like to focus on, as that is the high end enthusiast platform. A few months ago, there was a leak about Purley, which is Intel’s server variant o Skylake.

 

What would an ideal platform look like?

 

Characteristics of the ideal platform from Intel :

  1. At least 10 Skylake cores, likely in a “ring” configuration
  2. At least 1x (and perhaps 2x) 128 MB of eDRAM cache, which would act as an L4 cache
  3. Die soldered to the core
  4. At least 8 PCB layers on the substrate
  5. AVX512 on the desktop processors
  6. Six channel RAM
  7. X190 brings everything that the Z190 chipset brought
  8. 48 PCI-E lanes
  9. PCI-E 4.0 on the platform  (very unlikely at this point)

 

 

Let’s look at each of these in depth.

10 Cores of Skylake

Current leaks suggest that Intel’s 14nm parts will have 10 cores.  The rumour, originally sourced from Benchlife, should be considered with some degree of skepticism.

 

It is not however an unreasonable rumor and I think that it is plausible that a 14nm process could actually have 10 cores. The current top end product has 8 cores, the 5960X, which is Haswell E.  One counterargument though: I will  note that the jump from Sandy Bridge E (32 nm) to Ivy Bridge E (22 nm) did not see an increase in cores, which remained at 6. It was only with Haswell E that we enthusiasts saw a rise in the number of cores in the processors.

 

One potential pitfall of adding more cores is that more cores inevitably means lower overclocking headroom. Haswell E for example was around 300 Mhz slower than Devil’s Canyon, with the top Haswell E CPUs with 6-8 cores achieving overclocks of around ~4.7 Ghz (typically 4.4-4.6 GHz) versus 5 GHz (typically 4.7-4.9 GHz) on Devil’s Canyon with 4 cores. We should expect a similar penalty with Skytake E. The question is, will having 10 cores be somewhat slower than having 6 or 8 cores?

 

All in all, it is possible and I hope that it is true.

 

 

eDRAM

If you were to look at the reviews of the 5775C, one thing that you will note is that the CPU punches way above in several benchmarks what its IPC would suggest. That would imply that the eDRAM must be helping and acting as an L4 cache, even when the integrated graphics (iGPU) disabled.

 

Reportedly, Intel did not add Z170 eDRAM CPUs because the package size limit was 37.5 x 37.5mm (see interview with David Kanter at TechReport), but did so on mobile where the package limits were 42x42mm. I can only conclude that this was due to lack of space. There is considerable demand for a chip that has the eDRAM with full desktop grade power.  An LGA2011-sized socket, which is what we expect Intel to release for Skylake E would have the potential for a 128Mb eDRAM cache, assuming a similar package size to LGA 2011 (which is 52.5mm x 51mm). Granted, the die of an HEDT will be bigger, but I even then there should be some room afterwards.

 

Sadly, despite the gains, it remains questionable whether or not we will see an HEDT with eDRAM.

 

Soldered Die

For the past few generations of mainstream CPU, Intel has been using thermal paste rather than indium solder to hold the die onto the core. The end result has been that the CPU cores at full load can be as much as 25-35C (on Haswell) hotter than a delidded CPU, although this has been partially addressed in Devil’s Canyon (where delidding will yield around 15C lower temperatures at load).

I fully expect that like in previous generations of HEDT CPUs, Skylake E will be soldered and this will not be an issue.

 

At least 8 layers of PCB on the package

Skylake has cut the amount of PCB layers from 8 to 5, as user Splave has noted on Overclock.net. The fact that the substrate is thinner has caused damage to the PCB when heavier CPU coolers are used and to the pins. This appears to be a cost savings measure from Intel.

 

I do not expect this to be an issue on the Skylake E series and expect that like solder, the package will be identical to previous generations of HEDT CPUs.

 

AVX 512 for desktops

For sure Skylake E Xeon CPUs along with Intel’s Xeon Phi will get AVX 512. It is not however known if the consumer high end processors will at this time.

I could see some uses for applications that use the new extensions to the AVX instruction set benefiting from this. I hope that we see this on consumer CPUs.

My fear is that much like ECC memory, Intel might disable this on consumer CPUs and use it as a selling point for Xeons. Skylake mainstream did not get these extensions, although that is likely because it does not have the memory bandwidth to take advantage of it.

 

Six Channel Memory

Speaking of which, that brings us to memory bandwidth. The Purley leak saw six channel RAM. Combined with the stronger memory controller on Skylake for DDR4, we could see substantially higher bandwidth. Consumers could see >3400 MHz on desktop DDR4 like on mainstream Skylake – perhaps more as Skylake’s controller was limited by the need to support DDR3L. I don’t think that Skylake E will have any backwards compatibility to hurt DDR4 performance.

 

Currently we have 4 channels of RAM on the HEDT so 6 channels would bring a 50% improvement on top of the extra bandwidth of a stronger controller.  Certain applications limited by memory bandwidth could see some pretty huge benefits.  I suspect too that this will be needed for the AVX 512 instructions.

 

I think that it is certain that the Xeon line will get it. Whether consumers get it or not though remains to be seen. I just hope that Intel gives consumers both – the six channel RAM and the AVX512.

 

Everything Z170 brought

The Z170 chipset was a pretty significant upgrade over the previous Z97 chipset. DMI 3.0 was introduced, along with several other major features.

 

I fully expect that X190 will have DMI 3.0, along with everything that X99 brought to the table, such as 10x SATA ports. This is particularly important to me as the only alternative is the usage of third party chipsets. This current motherboard I am typing from, the MSI Z87 XPower is prone to bugs on the equipped Asmedia ASM1061 SATA controller. Controllers from Marvell, VIA, and other rival companies don’t work much better either. Even when they do work, the benchmarks show them to be substantially slower than a native solution.  I would prefer enough native ports so that such a solution is not needed.

 

To be honest, one thing I wish that Intel had was a “super chipset” with perhaps as many as 20x USB 3.1 ports, >10x SATA3 (perhaps some SAS), and sufficient DMI bandwidth to accommodate it all. I suppose that one can only dream.

 

PCI-E

Current leaks show the possibility of 48 PCIe lanes on the Purley leak. This is up from the previous variants of HEDT, which carried 40 PCIe lanes. I would say that this leak rumor is probable, but not assured.

 

Unfortunately the chances of getting PCIe 4.0 are looking slimmer. That may have to wait until the 10nm CPUs arrive, which are currently being delayed more and more. PCIe 4.0 is not relevant for GPUs (which are not PCIe 3.0 bottlenecked), but with the proliferation of NVMe SSDs, which can use the extra bandwidth, I can see a need for them in the upcoming years.

 

Conclusions

 

Although I do not expect to get all of the items on my wish list, I do expect that the majority will be satisfied.

 

I expect that Skylake-E will be a substantial update compared to Haswell-E and arguably a bigger update than what Skylake mainstream was to Devil’s Canyon.

 

I just hope that in the future, Intel will put a greater emphasis on the needs of the enthusiast community. Perhaps with the desktop market in decline and Intel struggling to gain a foothold in the mobile market, they will be forced to do so, especially if the demand for high margin server parts stagnates or worse, declines.

 

Likewise, I hope that AMD recovers with their Zen architecture. I have great confidence and admiration in AMD, but I wonder what they can accomplish. I hope that their team and the work done by Jim Keller produce something amazing though.

 

Until then, this Skylake-E platform has the potential to be a solid update for existing enthusiasts.

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